processor clock
英 [ˈprəʊsesə(r) klɒk]
美 [ˈprɑːsesər klɑːk]
网络 处理器时钟
双语例句
- As the name implies, this governor's goal is to get the maximum performance out of a system by setting the processor clock speed to the maximum level and leaving it there.
顾名思义，此调控器的目标的通过将处理器时钟速度设置为最大级别而实现最大的系统性能。 - The deeper the C state, the more power saving steps are taken& steps like stopping the processor clock or stopping interrupts from coming in.
CPU电源状态程度越深，采取的电能节省措施就越多&比如说停止处理器时钟或停止外部中断请求。 - For years, processor makers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.
多年来，处理器制造厂商在不断提高时钟速度和指令级并行性，因此单线程代码不需要修改就可在新的处理器上更快运行。 - An obvious solution is to use a processor with a faster clock rate, but for any given technology there exists a physical limit where the clock simply can't go any faster.
一个明显的解决方案是使用具有更快时钟频率的处理器，但是对于任何特定技术来讲都存在一个物理极限，时钟频率也有这样的极限。 - On some processors, for example, the count might be the cycle rate of the processor clock.
例如，在有些处理器上这个值可能等于处理器的时钟频率。 - The latency of memory is measured in nanoseconds as it is typically independent o n processor clock speed.
潜伏期的内存是衡量纳秒，因为它通常是独立于处理器的时钟速度。 - Unlike CISC processors, RISC engines generally execute each instruction in a single clock cycle, which typically results in faster execution than on a CISC processor with the same clock speed.
不像CISC处理器，一般的RISC引擎执行在一个时钟周期，每个指令，在快上具有相同的时钟速度的CISC处理器执行一般的结果。 - The first is new "multi-core" processor chips, in which performance is improved not by increasing clock speed, but by building several processing engines, or "cores", into each chip-a far more energy-efficient approach.
首先是新型“多核”处理器芯片，它在每个芯片中加入若干个处理器引擎或称“内核”来提高性能，而不是靠增加时钟频率。 - Other microcontrollers may serve performance-critical roles, where they may need to act more like a digital signal processor ( DSP), with higher clock speeds and power consumption.
其他微型控制器也许服务表现重要角色，他们也许需要行动更多象一个数字信号处理器（DSP），与更高的时钟速度和电力消费。 - The Application of PLL in the Design of Processor's Clock System
锁相环在处理器时钟设计中的应用 - The bus and the processor core often run in different clock frequencies, so their interface signals belong to different clock domains.
总线时钟与处理器内核时钟频率不同，因此总线部件与处理器内核间的接口信号需要进行时钟域转换。 - The asynchronous FFT processor controls the sequence of logic circuits by local handshake signals instead of the globe clock.
该异步快速傅立叶变换处理器采用本地的握手信号代替了传统的整体时钟。 - The method of expanding PS2 keyboard on the processor of ARM7 is discussed. The internal clock interruption and ex-interruption are used to realize the connection between the keyboard and the processor to expand the system agilely according to the system requirement.
讨论了为ARM7处理器扩展PS2键盘接口的的实现方法，分别利用内部时钟中断和外部中断两种方式实现键盘处理的原理和过程，目的是能够实现灵活地根据系统需求的扩展系统。 - In the first course of testing, the operating time of compare circuit is brought into play, synchronously, digital signal processor clock all the testing circuits 'operating time and keep these data in corresponding locations.
在每次测试第一次通电过程中，控制动作时间比较电路启动，同时数字信号处理芯片自动记录每一路的热敏电阻的动作时间数据，并进行处理。 - A testing device for solar irradiance measurements was described which consumed less power, this paper detailed the method of manufacture of the solarimeters and the construction of the data acquisition system consisting of a single-chip processor whose power was controlled by a real time clock.
本文介绍一种节电型的太阳辐射量测试装置，内容包括传感器的制作和用实时时钟控制的单片机数据采集系统。 - This article introduce the principle of Digital Signal Processor, specially refer to basic concept and design technique, include: instruction set, pipeline, memory organization, hardware interface, adder, multiplier, clock strategy, test technique.
阐述了数字信号处理器的原理，重点介绍了设计数字信号处理器芯片的简单概念及设计方法，包括指令集、流水线、存储器组织、硬件接口、加法器、乘法器、时钟方案、测试接口等等。 - According to different function, the hardware part is divided into processor module, analog signals input and converting module, digital signals module, communication module, clock module and display module.
按照功能的不同，硬件划分成处理器系统模块、模拟信号输入和转换模块、开关量输入输出模块、通信模块、时钟模块、键盘显示模块、电源模块。 - The first part, with DSP as the controller and processor, is used to receive and demodulate facsimile signal, It includes many circuit units, such as RF signal processing circuit, IF signal processing circuit, processor circuit clock circuit and power circuit.
其中，射频前端处理模块以DSP作为控制器和信号处理器，实现传真信号的接收控制和解调，包括射频信号处理电路、中频信号处理电路、处理器电路、时钟电路和电源电路。 - With the extensive application of high-definition video, The rapid increase of the video data has caused tremendous pressure to the computer central processor unit ( CPU), the method that increasing the CPU clock frequency to solve the problem has not obvious effect or not.
随着高清视频的广泛应用，视频数据量的剧增对计算机中央处理器（CPU）造成了巨大的计算压力，仅通过提高CPU的时钟频率来解决这个问题效果已经不明显或不可能。 - CPU core circuit include processor circuit, FLASH, SDRAM, network interface circuit, the standard JTAG interface, power supply circuit, reset circuit, clock circuit.
CPU核心电路的设计主要有处理器、Flash、SDRAM、网络接口电路、标准JTAG接口、电源电路、复位电路、时钟电路等的设计。 - The thesis details the under-controller and actuator design, including the core processor chip components of DSP, peripheral interface and clock circuits, the motor-driven, ADC and DAC circuit, feedback signal detections and power supply circuit.
论文中详述了下位机控制器和驱动器的设计，其中包括处理器DSP芯片的内核组成、外设和时钟电路、电机驱动、电机测速、A/D和D／A转换电路、反馈检测与供电电路等模块。 - The hardware frame of QCW radar signal processor is offered. the circuit of ADC module, FPGA module, dual-port RAM module and power and clock module is presented.
给出了编码二相调制准连续波雷达信号处理机的硬件设计框图，并对A/D转换模块、FPGA模块、双口RAM模块及电源和时钟模块进行了电路设计。